# Directions in parallel processor architecture, and GPUs too

- Institution: CERN
- Department: Computing Seminar
- Speaker: Olivier Giroux
- Year: 2014
- Language: English
- Subjects: Computer science
- Source: [CERN](https://videos.cern.ch/record/3005236)
- Licence: [CERN](http://copyright.web.cern.ch)
- Who can watch: Tweens profiles and older (sources give no ratings; placed by Invisible Network from the source's own words)

Modern computing is power-limited in every domain of computing. Performance increments extracted from instruction-level parallelism (ILP) are no longer power-efficient; they haven't been for some time. Thread-level parallelism (TLP) is a more easily exploited form of parallelism, at the expense of programmer effort to expose it in the program. In this talk, I will introduce you to disparate topics in parallel processor architecture that will impact programming models (and you) in both the near and far future.

About the speaker

Olivier is a senior GPU (SM) architect at NVIDIA and an active participant in the concurrency working group of the ISO C++ committee. He has also worked on very large diesel engines as a mechanical engineer, and taught at McGill University (Canada) as a faculty instructor. .

0:00:00 Slide 1

0:02:53 Slide 2

0:03:53 Slide 3

0:05:42 Slide 4

0:08:05 Slide 5

0:09:56 Slide 6

0:10:38 Slide 7

0:14:11 Slide 8

0:18:01 Slide 9

0:20:34 Slide 10

0:21:29 Slide 11

0:22:33 Slide 12

0:23:18 Slide 13

0:25:20 Slide 14

0:26:51 Slide 15

0:27:16 Slide 16

0:29:52 Slide 17

0:33:35 Slide 18

0:33:39 Slide 19

## Lectures

1. [Directions in parallel processor architecture, and GPUs too](https://invisiblenetwork.ai/learn/cern/3005236/40a3ee448dae), 1 h 12 min (CERN's player)